The present invention relates generally to a display apparatus which uses a simple matrix type liquid crystal panel. In particular, the present invention relates to a liquid crystal display device utilizing multi line selection addressing. In still further detail, it relates to a power supply structure with respect to a common driver and segment driver included in the display device.
Simple matrix type liquid crystal panels support a liquid crystal layer between orthogonally arranged and opposed row electrodes and column electrodes defining a plurality of pixels arranged in matrix form. Conventionally, the most relevant liquid crystal panel to this invention is driven by a voltage averaging method. This method selects each row electrode one at a time in sequence, and imparts a data signal corresponding to an ON/OFF display state to all column electrodes in accordance with a selected timing. As a result, the voltage applied to each pixel serves as a high application voltage only once (for a 1/N time period) during one frame interval, in which all the row electrodes (N electrodes) are individually selected sequentially, and during the remaining time period ((N-1)/N) a constant bias voltage is applied. When the response speed of the liquid crystal material used is slow, a change in brightness according to the effective value of the application voltage waveform in one frame interval may be observed. Consequently, when a frame frequency taking a large division number decreases, the difference between one frame interval and the response time of the liquid crystal becomes small, the liquid crystal respond to each applied pulse, and contrast in which flickering of the brightness appears, which is known as "frame response", is reduced.
A "Multi Line Selection Addressing Method" has been proposed as a manner of dealing with the problem of frame response, and is disclosed in, for example, Published Japanese Patent Application 5-100642. One example of a display device using a liquid crystal panel driven by this method is shown in FIG. 8. This multi line selection addressing method, by selecting a number of row electrodes simultaneously rather than conventional line by line selection, executes visible high frequency display and suppresses the above-described frame response. Since it selects a number of row electrodes simultaneously rather than selecting line by line, a means is required to obtain an appropriate pixel display. In other words, it is necessary to perform a calculation process on the original pixel data prior to applying it to the column electrodes. Specifically, a controller 101 is provided for producing orthonormal signals represented by the set of orthonormal functions, producing a sum of product signal in accordance with a result of performing a sum of product calculation with a set of the orthonormal functions and a set of selected pixel data. A common driver 102 applies a row driving waveform having a predetermined voltage level (+Vr, Vo, -Vr) to the row electrodes of a liquid crystal panel 103 by group sequential scanning in each selection time period, according to the orthonormal signals. Meanwhile, a segment driver 104 applies a column driving waveform having a predetermined voltage level (V1, V2, . . . Vn-1, Vn) to the column electrodes of the liquid crystal panel 103 in synchronization with the group sequential scanning, according to the sum of product signals.
To continue, the problems of conventional techniques will be briefly explained with reference to FIG. 8. Generally, while the common driver 102 and segment driver 104 for driving the liquid crystal panel 103 output a driving waveform of relatively high voltage level, the controller 101 performs only control with respect to the common driver 102 and the segment driver 104 and operates within a low voltage range in the same way as a normal IC. As a result, the conventional common driver 102 and segment driver 104 are connected with a high voltage power supply (V.sub.DD, -V.sub.LC), and the controller 101 is connected with a low voltage power supply (V.sub.DD, GND). The common driver 102 and segment driver 104 are high withstand voltage ICs, and the controller 101 is a low withstand voltage IC.
Incidentally, the voltage level of the row driving wave form output by the common driver 102 and the voltage level of the column driving waveform output by the segment driver 104 do not include mutually equal voltage ranges, but change depending on and relative to the main number of row electrodes simultaneously selected at each selected time interval. Where the simultaneously selected main number is small compared to the total main number of row electrodes, the range of voltage levels on the common driver 102 side becomes relatively wide and the range of voltage levels on the segment driver side becomes narrow. Conversely, where the simultaneously selected main number becomes relatively large with respect to the total number of row electrodes, the range of voltage levels on the common driver 102 side becomes narrow and the range of voltage levels on the segment driver side becomes wide. Despite the fact that range of required voltage levels of the common driver 102 and the segment driver 104 differ in this way, because both drivers are supplied in common by a high voltage power supply, high withstand voltage ICs have been used for both. For example, with respect to the controller 101 being able to use a normal IC having a withstand voltage rate in the vicinity of 5 V, the driver ICs required a withstand voltage rate in the range of 30 V. In manufacturing this type of high withstand voltage IC special structures and processes are required, which is a problem from a financial aspect. For example, with a high withstand voltage IC special processes such as thickening of the gate insulation film, etc. are performed. Also, special structures such as a double-layer diffusion drain and lengthened gate lengths, etc. are employed to raise the withstand voltage. The result of this is that the chip size is enlarged and the cost is raised by the increase in manufacturing processes. Further, it is disadvantageous due to the increase in consumption current accompanying the raising of the power supply voltage, generation of noise, and the like.